Exemplary embodiments of the present invention relate to a semiconductor package technology, and more particularly, to a technology for correcting an error of a memory chip mounted inside a package.
The current trend of electronic industries is to fabricate a semiconductor chip in a smaller size. Technologies for down-scaling the semiconductor chip include a system on chip (SOC) technology and a system in package (SIP) technology. The SOC technology is used to fabricate a plurality of semiconductor devices into a single semiconductor chip, and the SIP technology is used to package a plurality of semiconductor chips into a single semiconductor package. More specifically, the SIP technology is used to fabricate a single semiconductor package by mounting a plurality of semiconductor chips on a substrate horizontally or vertically.
In the early stages of semiconductor memory device development there were few defective cells in a memory chip after the semiconductor fabrication process. That is, a plurality of original good dies have been distributed on a wafer. However, because the capacity of semiconductor memory devices have increased, it has been difficult to fabricate a semiconductor chip having no defective cells. At present, it is rare to fabricate such a chip. To resolve such a situation, a repair method of replacing a defective cell with a redundancy memory cell has been used.
The repair is performed by storing an address of a defective cell, which is detected during a test operation, in a fuse circuit and internally replacing the defective cell with a cell corresponding to a new address. The repair is performed relatively easily at a wafer level. However, the repair is not easy at a package level, that is, after a wafer test and a repair are completed and a chip is mounted inside a package. In particular, even though no defects are detected during a wafer test, a new defect is occasionally detected after a chip is mounted inside a package. Therefore, there is a demand to repair an error which is detected or generated at a package level.
Further, it is more difficult to repair an error at the package level when a plurality of memory chips are mounted inside a single package. Therefore, there is a need for a technology which can repair an error at the package level even when a large number of chips are mounted inside a single package.